Capital Deepening Vs. Total Factor Productivity Under The India Semiconductor Mission 2.0 – IMPRI Impact And Policy Research Institute

Policy Update
Ritobrata Purkayastha

Background

The evolution of India’s technology policy reached a turning point with the transition from the foundational phase of the India Semiconductor Mission (ISM 1.0) to the expanded mandate of ISM 2.0. Launched in December 2021 under the Ministry of Electronics and Information Technology (MeitY) with a capital corpus of ₹76,000 crore , the program addressed physical deficits in domestic electronics manufacturing.

Post-pandemic disruptions in global supply chains, combined with heavy reliance on East Asia, exposed strategic vulnerabilities in India’s industrial architecture, which consumes billions of dollars in chips annually. The initial phase offered up to 50 percent fiscal support for greenfield front-end silicon fabs, display fabs, compound semiconductor units, and back-end assembly, testing, and packaging (ATMP/OSAT) facilities , approving 10 major projects with cumulative investment proposals of ₹1.60 lakh crore.

Building on these gains, ISM 2.0 was introduced in the Union Budget 2026–27, shifting focus from capital-intensive factory accumulation toward deep ecosystem consolidation. For FY 2026–27, the modified semiconductor program has a total financial outlay of ₹8,000 crore, including a dedicated ₹1,000 crore initial allocation specifically for ISM 2.0 ecosystem initiatives.

This phase targets the domestic manufacturing of fabrication equipment, processing of specialized raw materials (such as photoresists, masks, and wafers), development of indigenous intellectual property (IP), and industry-led research and workforce training. By targeting upstream nodes, ISM 2.0 transitions the domestic tech sector from capital deepening to a model driven by Total Factor Productivity (TFP) and domestic innovation.

Functioning

The institutional machinery of ISM 2.0 is administered by MeitY, operating under the Digital India Corporation. Under Article 246 of the Indian Constitution, high-tech manufacturing falls under central legislative entries, specifically Union List Entry 31 (strategic electronics) and Entry 52 (industries declared by Parliament to be of national importance).

Administratively, the mission operates across several core operational tracks:

• Semiconductor and Display Fabs Schemes: Provides up to 50 percent fiscal support on a pari-passu basis to absorb the high capital expenditures associated with greenfield front-end manufacturing.
• Design Linked Incentive (DLI) Scheme: Backed by a ₹1,000 crore outlay, this scheme supports domestic fabless startups and MSMEs by providing up to ₹15 crore per company for R&D, prototyping, and access to advanced electronic design automation (EDA) tools.
• Digital India RISC-V (DIR-V) Programme: Manages the development of an open-source, royalty-free processor portfolio to ensure tech sovereignty and lower licensing costs for domestic startups.

The domestic implementation of ISM 2.0 is structurally integrated with international supply-chain agreements. Under the U.S.–India Initiative on Critical and Emerging Technologies (iCET), India has established partnerships with dominant global tooling and training providers. Furthermore, bilateral supply-chain partnerships secure access to specialized chemical inputs, logistics corridors, and advanced packaging collaboration.

Performance

By mid-2026, the cumulative project pipeline under the semiconductor mission expanded to twelve approved manufacturing facilities across six states.

On May 15, 2026, the Cabinet approved two additional projects, including India’s first commercial Gallium Nitride (GaN) based Mini/Micro-LED display facility, introducing wide-bandgap materials capable of handling high voltages and frequencies. To support logistics, the central government notified a Special Economic Zone (SEZ) for Tata’s semiconductor facility in Dholera, Gujarat, on April 9, 2026, granting the site inland container depot status.

In the design ecosystem, the national chip design platform enabled approximately 2.25 crore EDA tool hours as of January 2026, supporting over 67,000 students and 1,000 startup engineers. Under the Chips to Startup (C2S) program, academic institutions taped out 122 designs and fabricated 56 chips at the 180nm node at the Semiconductor Laboratory (SCL) in Mohali. Startups completed 16 tape-outs, resulting in six chips fabricated at advanced foundry nodes as fine as 12nm.

A major design milestone was achieved with the launch of DHRUV64, India’s first homegrown 1.0 GHz 64-bit dual-core microprocessor. Developed by C-DAC on open-source RISC-V architecture, DHRUV64 is the third DIR-V chip to be fabricated, succeeding THEJAS32 and THEJAS64. DHRUV64 features an “out-of-order” execution engine and is capable of running full operating systems like Linux, positioning it for 5G Small Cells, Open-RAN systems, and smart grids.

SCL Mohali is also undergoing a comprehensive modernization drive. Earmarked for ₹900 crore in the FY 2026–27 Union Budget as part of a broader ₹4,500 crore upgrade plan first announced in November 2025, SCL aims to scale its 200 mm wafer line, increase output capacity by 100 times (targeting 1,500 wafer starts per month, up from 500-600 WSPM), and introduce GaN-on-silicon capabilities.

Impact

To evaluate the long-term economic viability of the India Semiconductor Mission, physical factor accumulation—capital deepening—must be compared against improvements in resource efficiency, measured as Total Factor Productivity (TFP).

Growth decomposition studies of the Indian economy from 1990 to 2023 show that while output per worker grew at a median rate of 4.71 percent annually, TFP contributed only 1.19 percentage points. The primary driver was capital deepening, contributing 1.91 percentage points, indicating that India’s industrial growth remains highly dependent on capital accumulation rather than systemic efficiency gains.

This relationship is conceptually grounded in the standard Solow-Swan neoclassical production function, which defines labor productivity as output per worker and capital intensity as physical capital per worker. In this framework, labor productivity growth is driven by two distinct economic mechanisms: capital deepening (which increases physical machinery per worker) and TFP growth (representing pure technological progress, organizational innovation, and efficiency gains). While capital deepening increases labor productivity, it is subject to diminishing marginal returns; without concurrent TFP growth, output growth will eventually decelerate.

This structural challenge is visible in high-tech global value chains, represented by Stan Shih’s “Smiling Curve,” which shows that value-added is concentrated at the upstream ends (such as R&D, design, and IP) and downstream ends (branding, services), while dipping below 5 percent gross margins in the midstream fabrication, packaging, and assembly stage. Under ISM 1.0, massive capital subsidies primarily targeted this low-margin midstream segment (capital deepening). While increasing physical output, these do not automatically translate into TFP gains if the upstream inputs and downstream branding remain controlled by foreign entities.

The transition to a semiconductor manufacturing presence is further explained by the “Productivity J-Curve” hypothesis. This model suggests that major structural transformations or new general-purpose technologies can initially cause a decline in measured TFP growth due to high gestation lags of massive capital investments, resource diversion for learning complex process recipes, and deteriorating early-stage capacity utilization. Once firms adjust, adapt, and build local expertise, the economy climbs out of the J-curve valley, and TFP begins to rise through learning-by-doing and scale economies.

ISM 2.0 is designed to accelerate this transition and raise the domestic manufacturing curve. By focusing on semiconductor equipment, advanced materials, and local IP, the policy targets the high-value upstream segment of the Smiling Curve. Developing open-source, royalty-free microprocessors like DHRUV64 directly enhances the efficiency parameter by allowing domestic startups to design custom chips without paying licensing fees to foreign firms, lowering transaction costs, encouraging local innovation, and generating more value-added from the same input factors.

Emerging Issues

Despite the strategic focus of ISM 2.0, several structural challenges persist:

• Coordination Risks in SCL Mohali’s Public-Sector Model: Backed by a ₹4,500 crore modernization drive, state-run SCL in Mohali aims to transition from a legacy research unit into a source of mature-node chips. However, this modernization is divided into three separate packages: equipment procurement, design enablement, and automated line management. Analysts warn that this fragmented structure poses significant coordination risks, unlike standard semiconductor execution models which rely on integrated program and product teams, risking “blame loops” between different vendors if yields fall short.
• SCL’s Strict Sourcing and the Refurbished Tool Dilemma: SCL Mohali’s strict RFP guidelines require all utility infrastructure modifications to use new equipment, while refurbished manufacturing tools must carry OEM support for at least ten years and possess a minimum residual life of 80 percent at shipment. These requirements clash with global refurbished equipment market realities, where tools are often sold without long-term OEM guarantees. This strict approach, driven by concerns over high annual maintenance costs (SCL reportedly spends ₹127 crore annually on repairs), risks delaying tool installation and inflating overall modernization costs.
• Talent Retention and the “Upskilling Pipeline” Risk: SCL and other public institutions face severe talent retention challenges. Public facilities risk becoming taxpayer-funded upskilling pipelines for private fabs unless retention incentives, career pathways, and salary structures are improved to match private domestic firms or multinational design houses.

Way Forward

To successfully transition from raw capital deepening to sustained Total Factor Productivity gains, the implementation of ISM 2.0 should focus on several key areas:

1. Establish a Domestic Productization Unit: Establish a shared “productization unit” to help early-stage startups translate chip layouts into process-specific manufacturing recipes, analyze wafer data, and manage foundry interfaces, reducing design failures and accelerating the transition from prototype to commercial silicon.
2. Grant Operational Autonomy to SCL Mohali: SCL must have the autonomy to execute fast-track budgets and sign long-term service contracts with tool manufacturers to bypass standard, slow public-sector procurement cycles.
3. Implement Talent Retention Frameworks: This includes introducing specialized technical career tracks matching private-sector salaries, performance-linked bonuses, and formal service-term commitments for engineers undergoing advanced training on state-of-the-art public tools.
4. Create a Single-Window Interface: Introduce a single-window digital interface to manage the entire workflow—spanning design verification, multi-project wafer (MPW) scheduling, fabrication, and back-end packaging.
5. Streamline Sourcing Regulations: Establish clear HS codes specifically for specialized semiconductor machinery, spare parts, and chemical inputs to streamline customs clearance. Introducing structured flexibility in SCL’s refurbished equipment guidelines aligned with the Foreign Trade Policy 2023 can utilize high-residual-life refurbished machinery to build cost-effective cleanrooms and training fabs, managing project costs while accelerating ecosystem ramp-up.

Selected References and Important Links

• Ministry of Electronics and Information Technology (MeitY): Official Portal
• India Semiconductor Mission (ISM): Official Portal
• Press Information Bureau (PIB), (2026). India Semiconductor Mission 2.0: A Major Push in Budget 2026 towards Semiconductor Self-Reliance. ((https://static.pib.gov.in/WriteReadData/specificdocs/documents/2026/feb/doc202627782101.pdf))
• Virmani, A., & Hashim, D. A., (2011). J-Curve of Productivity and Growth: Indian Manufacturing Post-Liberalization. IMF Working Papers, 2011(163). (IMF eLibrary)
• Carnegie Endowment for International Peace, (2025). Revisiting the Usage of Refurbished Equipment in India’s Semiconductor Ecosystem. (Carnegie Link)

About the Contributor

Ritobrata Purkayastha is a Research & Editorial Intern at the IMPRI Impact and Policy Research Institute, New Delhi. He is currently pursuing a Bachelor of Science (B.Sc.) in Economics (3rd Year) at XIM University, Bhubaneswar. His research interests encompass monetary econometrics, public policy, and the application of data science and quantitative econometric tools to socio-economic challenges.

Acknowledgements

The author sincerely expresses gratitude to the reviewers Kavin Adithya and Ameya Satnam  for their valuable comments, constructive suggestions, and continuous guidance throughout the preparation of this article. Their insightful feedback significantly enhanced the clarity, organisation, and analytical quality of the manuscript. The author also acknowledges the support and encouragement received during the research and writing process, which contributed to the successful completion of this work.

Disclaimer

All views expressed in the article belong solely to the author and not necessarily to the organisation.

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