Policy Update
Rounak Panda
Background
The Ministry of Electronics and Information Technology (MeitY) launched in 2014 the Special Manpower Development Programme for Chips to System Design (SMDP-C2SD). It was an extension under the broader Digital India initiative, which is deemed an important societal and developmental intervention. It was framed as a technical capacity-building programme but also bridges deeper challenges concerning technological sovereignty, educational inequities, and national innovative capacity.
The programme aims to cater to India’s strategic need for autonomy in the field of semiconductors and embedded system design, which has been historically dominated by external expertise, and also caters to the larger societal imperative of expanding participation in the digital economy. It seeks to address the severe shortage of skilled manpower in VLSI (Very Large-Scale Integration) design and system-level engineering, which otherwise hampers economic competitiveness and individual capacity building.
Building on earlier government efforts in skilled manpower development initiatives, SMDP-C2SD aims to democratize access to high-end technical knowledge by providing students and faculty across undergraduate, postgraduate, and doctoral levels with expertise in VLSI, embedded systems, and Electronic Design Automation (EDA) tools. The beneficiaries are selected from a pool of partner academic and R&D institutions, which are key actors in consolidating India’s indigenous technological ecosystem. In India’s evolving digital society, SMDP-C2SD envisions technological advancements which are inseparable from social empowerment, by promoting personal opportunity and collective resilience.
Objectives
SMDP-C2SD pursued numerous objectives aimed at holistic technical advancement and addressing socio-economic needs.
| Objective | Technological Focus | Developmental Relevance |
| Train VLSI/Embedded engineers | Specialized courses (VLSI, SoC, Embedded) | Build human capital for a knowledge economy; reduce dependence on foreign-trained engineers |
| Create IP cores | Indigenous digital designs (processors, controllers, communication modules) | Strengthen India’s position in global value chains; generate IP-led wealth |
| Upgrade labs and tools | Installation of EDA suites across 60+ institutions | Decentralize access to high-end design infrastructure beyond metro cities |
| Facilitate MPW Access | Shared prototyping at advanced technology nodes (65nm, 45nm) | Democratize innovation; allow students and researchers to create real silicon |
| Build Industry Linkages | Collaborative projects, internships | Improve employability, link academic skills to market needs |
| Strategic autonomy | Secure, indigenous design pipelines | Ensure national resilience in defense, critical infrastructure, and future industries |
Every technical action taken under SMDP-C2SD was a calculated move to create an inclusive technological citizenship, empowering smaller universities and opening up opportunities for young researchers to contribute to India’s semiconductor journey.
Functioning: How SMDP-C2SD Operationalized Its Vision
SMDP-C2SD was implemented as an integrated national program to address four systemic gaps critical to India’s semiconductor environment.
Human Capital Formation
- More than 13,000 trained across B.Tech, M.Tech, and PhD levels (2015-20210)
- Training included experiential learning through the project in SoC, ASICs, FPGA prototyping, and embedded system design.
- Faculty Development Programs (FDPs), workshops, and seminars are strengthened across institutions.
These interventions tackled the acute shortage of skilled professionals in VLSI and integrated systems. Inculcating advanced skill development within academic networks has democratized access to high-end technical education.
Infrastructure Creation
- More than 60 institutions equipped EDA Tool Suites such as:
| Tool Category | Example Tools | Functional Purpose |
| Analog/Mixed-Signal Design | Cadence Virtuoso | Custom IC Design |
| Digital RTL to GDSII Flow | Synopsys Design Compiler, IC Compiler | Physical chip realisation |
| Verification and DRC | Mentor Graphics Calibre | Layout rule checking and quality assurance |
- Approximately ₹18 crore has been invested between 2014 and 2021 exclusively in tool licenses.
- It is based upon a hub and spoke model, in which a premier institute acts as a hub and provides technical know-how to different institutes under the program acting as spokes
Under this program, cities like Bhubaneswar, Surat, and Silchar got state-of-the-art VLSI labs, extending technical capacity beyond premier institutions like IITs, promoting regional technology equity.
Indigenous Research and IP Development
- More than 280 research projects were funded across participating institutions.
- More than 65 validated IP cores developed, including:
- Low-power ADCs
- RISC–based microcontrollers
- Wireless communication Ips
- An estimated more than 520 publications/patents emerged from program-supported research.
Each SMDP-C2SD IP core developed gives a boost to India’s growth from technology consumption to creation. Institutional support for applied research and innovation assists in the development of long-term intellectual property assets, minimizing reliance on foreign designs.
Prototype Fabrication through MPW Access
- 8 Multi-Project Wafer (MPW) runs enabled at 65nm and 45nm nodes through collaborative efforts with international foundries.
- Process: Design submission (by student/faculty teams) → GDSII file aggregation by C-DAC → Foundry fabrication → Chips returned for testing and validation.
- More than 45 institutes participated
By offering physical access to actual silicon fabrication at a fraction of the usual cost (80-90%), SMDP-C2SD broke down long-standing Indian academic barriers. For many first-generation engineers, this was their first chance to turn designs into functional silicon – a significant transition from theory to reality that considerably boosts career paths and innovation potential.
Performance Evaluation
Evaluating the performance of SMDP-C2SD involves examining the combination of quantitative outputs, institutional coverage, and budgetary outlays, as indicated by MeitY, C-DAC, and PIB releases in the past few years.
| Key Indicator | Details | Figures / Output | Source |
| Students Trained | Trained across UG, PG, and PhD levels in VLSI, embedded systems, and EDA tools | 13,000+ | MeitY Annual Reports |
| Broader Skill Development Expenditure | Includes SMDP-C2SD and related semiconductor skill initiatives | ₹298+ crore (10 years) | PIB Release, Dec 2024 |
| Annual Govt. Expenditure (Skill Development) | Under semiconductor capacity-building efforts incl. SMDP-C2SD | -₹38.90Cr (2022–23) -₹28.95Cr (2023–24) -₹69.84Cr (till 2024–25) | PIB Release, Dec 2024 |
| Centers of Excellence | Academic & R&D institutions supported with infrastructure and training tools | 60+ | C-DAC |
| EDA Infrastructure | High-end tools installed (e.g., Cadence Virtuoso, Synopsys, Mentor Graphics) | ₹18 crore (EDA licenses) | MeitY, C-DAC Reports |
| Research Projects Funded | Design and semiconductor-focused research grants | 280+ | C-DAC |
| IP Cores Developed | Indigenous IPs in ADCs, microcontrollers, wireless protocols | 65+ | MeitY |
| Start-ups Supported | Start-ups incubated or supported through academic linkage | 18+ | MeitY |
| MPW (Siliconization) Runs | Real chip fabrication access at 65nm/45nm nodes through international foundries | 8 MPW runs | C-DAC |
| Institutions Participated (MPW) | Academic institutions submitting GDSII files for fabrication | 45+ | C-DAC |
Impact: Building Indian Semiconductor Ecosystem
The SMDP-C2SD has helped India’s semiconductor industry giant leap forward. The program developed the nation’s first large-scale talent pool of VLSI and embedded system design-trained engineers, many of whom now contribute to indigenous R&D and innovation in academia as well as new startups. The human capital investment was strategic in directly targeting the talent gap in chip design and high-end electronics, enabling people to contribute effectively in high-tech field.
The infrastructure enhancement of the partnering institutes has become a long-term societal asset, promoting experiential learning and applied research across geographies, particularly in Tier 2 and Tier 3 cities. The programme has contributed significantly to decentralised high-tech R&D from metro clusters to an inclusive and diverse innovation geography.
The ripple effects can be seen in the industry and national strategy. Companies like Signalchip, which created India’s first 4G/5G, have benefited from SMDP-C2SD-trained talent. The program’s efforts also laid early foundations for microelectronics innovation in strategically sensitive areas, including defence technologies.
Anthropologically, the programme remapped the boundaries of technological engagement in India from elite-led innovation to a more democratized society-focused model. It triggered a cultural transformation towards experiential, design-inspired engineering education, which is key to fulfilling the vision of the Semicon India mission. Essentially, the program positioned India not just as a consumer of advanced technology but as a capable originator within the global semiconductor value chain.
Emerging Challenges in SMDP: C2SD Implementation
| Issue | Development Concern | Suggested Remedy |
| Limited IP Commercialization | Risk of “paper IPs” not translating into deployable products due to a lack of downstream industry engagement | Establish a National IP Licensing Platform to vet, package, and broker academic IP to MSMEs/startups |
| Insufficient Industry Absorption | Skills mismatch between graduates and industry needs, leading to underutilization of trained manpower | Mandate industry co-supervised student projects and frequent industry-led curriculum reviews |
| Curriculum Adaptation Lag | Academic programs lag behind rapid advances in semiconductor design methodologies and tools | Institutionalize agile curriculum updates, modular short-term courses, and faculty-industry exchanges |
| Faculty Expertise and Retention | Difficulty in attracting/retaining VLSI-trained faculty due to better compensation in the private sector | Introduce competitive faculty incentives, industry sabbaticals, and advanced upskilling opportunities |
| Infrastructure Duplication | Redundant spending on tool licenses and hardware across institutions with overlapping capabilities | Implement a National EDA Cloud with centralized access to licensed tools and remote lab environments |
| Equitable Access and Tool Utilization | Students in smaller or remote institutions lack consistent access to high-end design tools and technical support | Roll out cloud-based EDA access, standardized tool training modules, and regional support cells |
| Lack of Domestic MPW Services | High cost of silicon prototyping and dependence on foreign foundries limit the design-to-product transition | Develop an Indian MPW fabrication facility under the India Semiconductor Mission (ISM) |
| Bridging the “Chip-to-System” Gap | Gaps in training for system-level integration, embedded software, and real-world application design | Fund interdisciplinary system prototyping projects, promote hardware-software co-design modules |
Way Forward
- SMDP-III (2022–27) must shift towards 21st-century needs: AI chips, RF Systems, Quantum Processors.
- Strengthen Regional Capacity: Focus on empowering Tier-2 and Tier-3 institutes.
- Align with Strategic Sectors: Defence, Healthcare, Automotive Electronics.
- Public–Private Partnerships: Co-create innovation labs with industry stakeholders.
- Global Collaboration with Indian Anchoring: Leverage foreign training while ensuring knowledge retention within India.
- PLI schemes to boost manufacturing in India.
Conclusion
SMDP-C2SD has been instrumental in creating the foundation of India’s semiconductor design ecosystem by developing skilled manpower, decentralizing infrastructure, and promoting indigenous IP creation. Over and above its technical success, the program embodies a strategic paradigm shift towards self-reliance, inclusive innovation, and knowledge-based development. In order to continue its influence, the subsequent phase needs to emphasize commercialization, more intense industry linkages, and regional equity—positioning India as a global design hub with profound developmental roots.
Reference
- C-DAC. (2023). SMDP-C2SD annual review report. Centre for Development of Advanced Computing.
- Ministry of Electronics and Information Technology (MeitY). (2024). Annual report 2023–24. Government of India. https://www.meity.gov.in/writereaddata/files/Annual_Report_2023-24.pdf
- Press Information Bureau. (2024, December). Achievements under the Digital India Initiative. https://pib.gov.in/PressReleasePage.aspx?PRID=1987452
- Ministry of Electronics and Information Technology (MeitY). (2022). Semicon India Programme guidelines. Government of India.
- NITI Aayog. (2021). Building India’s semiconductor ecosystem: A policy overview.
- Raghavan, A. (2023). VLSI education in India: Policy, practice, and performance. Economic and Political Weekly, 58(14), 42–50.
About the Contributor
Rounak Panda, Research Intern, IMPRI. Currently pursuing B.Sc (Hons) Economics at Dr. B R Ambedkar School of Economics – University, Bengaluru.
Acknowledgement
The author extends his sincere gratitude to the IMPRI team and Ms. Aasthaba Jadeja for her invaluable guidance.
Disclaimer: All views expressed in the article belong solely to the author and not necessarily to the organisation.
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